Solution improves multi-functional printer SoCs design development
In order to improve the development of its multi-functional printer SoCs, Fuji Xerox used Cadence Design Systems' Cadence Genus Synthesis Solution. The Cadence solution enabled Fuji Xerox to reduce its timing closure schedule more than 50% and achieve up to 16% area reduction for its sub-blocks, resulting in an eight percent total chip area reduction when compared with its previous solution.
Fuji Xerox employed the Genus Synthesis Solution’s innovative early physical flow, which rapidly models physical effects such as placement and routing from the earliest stages of logic synthesis. This capability helped them minimise gate area of SoC while also meeting performance targets, which led to improved power, performance and area (PPA) and faster time to market.
Additionally, the Cadence solution’s accurate physical effect modeling improved performance correlation to place and route, which allowed Fuji-Xerox design engineers to close the design more easily, reduce the turnaround time (TAT) iterations with their ASIC vendor and shorten the overall development schedule.
“Our customers are requesting that we support more value-added features for multi-functional printers, which means that SoC development has become more and more complex,” said Noriaki Tsuchiya, ASIC Design Group Manager, Controller Platform Development 1, Software Development Group, Fuji Xerox. “The Genus Synthesis Solution’s area and timing optimisation engines addressed our design quality and TAT requirements, and we’ve saved on our SoC design engineering resources. Given our successes with the Cadence solution, we plan to continue using it and evaluate the Genus physical optimisation flow to further optimise PPA with our next-gen SoC designs.”
The Genus Synthesis Solution is a next-gen RTL synthesis and physical synthesis engine that addresses the productivity challenges faced by SoC designers. It is a part of the Cadence digital design platform that supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.