The re-architected rapid recompile feature allows users to make small changes to their design and recompile in a fraction of the time versus doing a full compile. Using rapid recompile, designers will experience a speed up of up to 3X for pre-synthesis HDL changes and up to 4X for post-fit SignalTap II logic analyzer modifications, while preserving placement and routing for the unchanged portion of the design. Rapid recompile now supports all 28 nm Cyclone V, Arria V and Stratix V FPGAs.
Altera’s PCIe solution boosts application performance by delivering up to 6.7 GB/s throughput and greater than 400K input/output operations per second (IOPS). The solution includes a newly architected DMA engine, enterprise-ready device drivers and reference designs that simplify the evaluation and design integration process.
Enhancements to the Qsys system integration tool simplify the process of connecting system-level hardware components. Qsys expands its support for the AMBA AXI3 and AXI4 specification to include support for AXI4-Lite, a light-weight version of AXI4, and AXI4-Stream, for point to point connections. These enhancements enable better design reuse by supporting a broader range of custom IP and easing integration with Altera and third-party developed IP.
Alongside the update to the Quartus II software, Altera have also released updates to the Altera SDK for OpenCL version 14.0. This latest release includes a rapid prototyping design flow that allows programmers to prototype designs on an FPGA accelerator board in minutes.