Design

Silicon-proven DesignWare Interface IP to accelerate SoCs

23rd July 2020
Alex Lynn

Synopsys has announced that JLQ Technology has selected Synopsys DesignWare Interface IP to accelerate development of its new generation of high-performance, low-power systems-on-chips (SoCs) for a range of applications.

JLQ chose Synopsys' silicon-proven DesignWare IP, including USB, MIPI, DDR, and more, due to Synopsys' established track record of providing high-quality IP solutions that have enabled JLQ to deliver the best combination of performance, power, and area for their target applications.

JLQ Technology develops mobile chips and solutions, as well as SoCs for intelligent IoT products including smart cameras, smart players, and industrial robots to contribute to the development of a more connected world.

"As we grow into a world-class fabless semiconductor company, we rely on high-quality IP to help us lower our design risk, differentiate our SoCs, and accelerate our time-to-market," said Liang Chen, Vice President of Project Engineering at JLQ Technology. "Our collaboration with Synopsys through the years has enabled us to successfully build highly competitive products that are shipping in volume. We selected Synopsys, the leading provider of interface IP, due to their unmatched technical expertise and responsive local support infrastructure."

"Synopsys is at the forefront of providing high-quality IP solutions that give designers a competitive edge in their markets," said John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys. "As the leading provider of interface IP, Synopsys is an active contributor to all of the major standards bodies, helping to drive wide adoption of new protocols and enabling designers to integrate the necessary functionality into their designs with significantly less risk."

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