An integral part of PCB

7th November 2012
ES Admin
Signal integrity simulation before, during and after PCB design is now one of the most underestimated tasks in electronics product development. Jörg Kaleita, Technical Account Manger from Altium Europe explores and discusses signal integrity simulation in this article from ES Design Magazine.
Developers often rely on rules of thumb to manage the risks of signal reflections and crosstalk sufficiently and without much extra effort. But does this approach meet the requirements of today’s electronic devices?

To answer this question, we need to first look at the basic physics of the phenomenon of reflection on transmission lines. During their studies many engineers may have learned that the world is binary; there are only two possible states: ‘0’ and ‘1’, a view that makes little mention of analogue technology. A binary signal is characterised by smooth transitions from 0 to 1 and 1 to 0. Oscillation due to signal reflection from the receiver is not an issue that comes up in this context.

For low-speed technologies, such as TTL with about 5ns switching times, this may not be a problem. As a rule, at these rise times, signal integrity deteriorates only slightly due to reflection at the receiving end. So why spend extra effort on simulation? The answer is simple; because time does not stand still and smaller semiconductor structures often result in shorter rise and fall times. These then result in reflections, which in turn lead to signal overshoot or undershoot. If, for example, you have a numerical 2.5V signal and get an overshoot of up to 4.5V, this could well be the last reflection at the receiving end because the ESD diode at the sending end may have gone bust. An undershoot of up to 1.5V, on the other hand, could easily mean that the receiver is clocked twice, leading to even more uncomfortable consequences because an error like this is hard to find.

In the following a typical rise time of 0.3ns is assumed, which many modern drivers can reach without a problem. To determine reflection on a transmission line it is further necessary to establish the Transitional Electrical Length (TEL). This is defined as the velocity of an electromagnetic wave – when using a particular material – multiplied by the signal rise or fall time. To put it another way it is the signal change itself that counts, not the number or frequency of changes. When using FR4 PCB materials, speeds of 15cm/ns – about one-third the speed of light – are standard. Accordingly, with our assumed rise time of 0.3ns multiplied by 15cm/ns, the TEL is 4.5cm.

Proven rules of thumb

Developers apply many rules of thumb in their daily practice. One of these states that reflections are likely to occur when a transmission line is more than 20 percent longer than the calculated TEL. In our case, this would be exactly 9mm. Now the engineer must ask themselves the question ‘how many tracks in this PCB design are longer than 9mm?’ One of the most common misconceptions about signal integrity is the belief that reflections depend on frequency. Unfortunately that is wishful thinking.

This should answer the question about whether to investigate these phenomena; what remains is the question of how a developer can ensure they will discover these faults without too much effort in order to avoid in-field failures. The unified development environment Altium Designer offers an interesting solution, because signal integrity simulation is an integral part of the package and needn’t be purchased separately. Another advantage of this solution is that it doesn’t simply integrate a simulation tool into a collection of point tools. Instead, this simulation has access to the information in the unified database that can be used by all other processes – including the PCB design process.

Once the developer has routed the board, the simulation tool has access to almost all the data needed – including nets, layer stack, track length and pin spacing. If an appropriate IBIS model has been assigned to the used components in advance, simulation can go ahead. It is however advisable to specify another rule which permits tolerances of ± 20%. At the push of a button all nets are examined for compliance with the specified tolerances.

After simulation, the status of all nets is clearly displayed in a control window

Once simulation is complete, the status of all nets is displayed clearly in a control window in line with the set standards. If all signals have successfully passed the test, you can now turn to other tasks. Figure 1 shows the signal integrity control window.

If some signals did not pass the test, they and all nodes can be examined further for reflections. Since Altium Designer provides a unified development environment, it only takes a mouse click to identify and highlight these signals on the PCB or in the schematic. When using components with programmable I/O units (e.g. FPGAs), it is possible to stack the different curves to calculate the best driver strength. Figure 2 shows what the respective simulation window might look like.

Example of a simulation window which allows you to test for signal integrity

Because a complete FPGA development environment has been integrated into the design environment there is no need to switch to another tool, for example when matching driver strength and simulation. Whenever the driver strength cannot be changed, the developer has the option of using a serial resistor for signal attenuation. Various termination models are also integrated, making it simpler to determine the best resistance value.

Many PCB designers also have some aesthetic demands for their designs. For this reason, bus structures are often routed together. This looks beautiful, but carries the risk of crosstalk. The unified development environment provides an easy solution: at the touch of a button, you can identify all tracks that meet the given search criteria (e.g. maximum 10mm spacing and minimum 10mm parallel tracks) and analyse for crosstalk from one aggressor channel to another without a problem.

Signal integrity starts prior to simulation

More and more standards shift responsibility for the proper functioning of semiconductor devices to the routing process. It is therefore adamant to comply with the specifications of the relevant data sheet, because otherwise even the best simulation tool will be of no use. For example, if using a DDR memory, it is absolutely necessary to match the data and clock trace lengths. Here’s a list of some possible scenarios:
-Match lengths for interconnects in simple bus structures (e.g. DDR3 memory).
-Match lengths for differential interconnects (e.g. Gigabit Ethernet).
-Impedance-driven tracks (e.g. 50Ω).
-Two memory banks on a driver component (stubbed T-Nets).
-Resistors for attenuation in interconnects need to be matched.

When routing interconnects with Altium Designer, length matching functions for simple and differential interconnects are already integrated. After routing, a tolerance value is usually set for the respective nets. This is later used for length tuning and wave lines are added up to the set specifications. Interconnect impedance is largely determined by line width and layer stack. In Altium Designer you simply set a rule for the respective interconnects to calculate the line width and layer stack from the specified data in the unified database.

With so-called stubbed T-Nets, length tuning is not quite as simple because this requires matching the lengths of both driver output and receiver input. If the same components are used for the receiver, the two tracks are usually of equal length. When input capacitances vary, a runtime difference will occur over different lengths, which should first be simulated. A common problem with this approach is the segmentation of the nets. Since the net is to be divided into three segments and each segment is assigned a net name, the tool will report an error leading to a short circuit.

The concept of ‘net ties’ can provide a solution here; it can also be very useful when physically connecting digital and analogue mass. The developer defines an arbitrary component in the library editor and assigns ‘net tie’ in the relevant properties. It is possible to set a rule for the component to appear in the bill of materials or not. This method avoids any rule violations and each segment can be adjusted in length.

The opposite scenario occurs when routing track with a resistor. In this case, you have a net before and after the resistor, which makes any length adjustment significantly harder. A little trick can help, however; briefly short circuit the used resistor in the schematic as shown in Figure 3.

Short circuiting the attenuation resistor simplifies length adjustment

If you highlight the respective track in a particular colour – as is recommended – you can later delete it using the colour selector in the Find Similar menu. As the colour coded nets in Figure 3 show, short circuiting means there is only one physical net making length adjustment a mere formality. You can now place the 0402 resistor on the PCB as desired and route the track to both connectors. After length adjustment you can then calculate an appropriate resistor value with the simulator. The segments between the connectors can be selected or deleted. The short circuits are deleted in the schematic, and the calculated value is entered for the resistor. After final comparison with the PCB design two nets are again in place.

In conclusion it is clear there are some good ways of readying your board for high speed design. For example, by individually determining the via layer stack, routing the tracks in curves (including buses) and equipping the pads with so-called teardrops.

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