Design

Sign off tools speed up 16 nm ASIC chip tapeout

5th June 2019
Mick Elliott

Full-flow digital and signoff tools from Cadence were used by Socionext for the successful production tapeout of its latest large, 16nm ASIC chip and it has built a design environment for its 7nm designs. Using the capabilities of the integrated full flow, Socionext sped design closure on its 16nm design when compared with its previous solution.

The Socionext certified flow for the 16nm and 7nm designs includes the Cadence Genus Synthesis Solution, Cadence Conformal Equivalence Checker, Cadence Innovus Implementation System, Cadence Quantus Extraction Solution, Cadence Tempus Timing Signoff Solution, Cadence Voltus IC Power Integrity Solution, and Cadence Physical Verification System (PVS).

In particular, the Tempus Timing Signoff Solution enabled the Socionext team to meet design productivity goals for its 16nm production designs by using the Tempus SmartScope hierarchical models.

The Tempus SmartScope models facilitate hierarchical static timing analysis (STA) signoff and signoff-accurate engineering change orders (ECOs) by letting users dynamically abstract portions of the design so they can analyze blocks with accurate chip-level context.

Additionally, the Voltus IC Power Integrity Solution enabled Socionext to reduce electromigration (EM) analysis turnaround time by 60 percent, which is critical for 16nm and below FinFET process technologies.

For Socionext’s 7nm design, the Innovus Implementation System’s Flex H-Tree capability in particular has already proven to be critical in enabling power, performance and area (PPA) benefits.

The Flex H-Tree is an advanced clock synthesis technology that enables users to consider floorplan blockages and power tradeoffs, allowing Socionext to meet its target goal for clock skews.

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