Meridian DFT identifies DFT trouble spots to allow designers to optimize testability during Register Transfer Level (RTL) creation, when the design impact is the greatest and the cost of modification is the lowest. It offers what-if analysis for DFT trade-offs and predicts Automatic Test Pattern Generation (ATPG) coverage of stuck-at and at-speed tests. Meridian DFT is designed to work with any ATPG or synthesis tool. It helps designers achieve high test quality and fault coverage at the RTL.
“Real Intent’s strength is in providing surgical solutions for important design verification problems,” commented Pranav Ashar, Chief Technology Officer of Real Intent. “We are introducing Meridian DFT to check the pre- and post-synthesis RTL for testability and DFT-related implementation errors. As with the other Real Intent tools, we fully expect that our recipe of marshaling formal methods, structural analysis and simulation will allow Meridian DFT to meet our customers’ needs.”