Design

Prototyping platform reduces design bring-up time by 80%

28th February 2017
Alice Matthews

Cadence Design Systems has announced the new Protium S1 FPGA-based prototyping platform, which incorporates implementation algorithms to boost engineering productivity. The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform, thereby delivering 80% faster design bring-up on average when compared to typical FPGA prototyping approaches.

Utilising Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

"The Cadence Protium S1 platform ensures scalability to hundreds of software developers at the earliest possible point during the development flow and allows developers to focus on design validation and software development rather than prototype bring-up,” said Peter Ryser, Senior Director for System Software, Integration and Validation at Xilinx. The common flow with the Cadence Palladium Z1 emulation platform enables a smooth transition from emulation to prototyping, which greatly improves productivity.”

“As a leading supplier of Ethernet and InfiniBand intelligent interconnect solutions and servers, storage and hyper-converged infrastructure, the complexity of our designs is constantly increasing and requires rigorous verification,” said Alon Webman, Vice President of Silicon Engineering at Mellanox Technologies. “Cadence’s Protium S1 platform provides world-leading congruency with their Palladium Z1 emulation platform, allowing us to optimise the balance between emulation and FPGA-based prototyping. We use the Protium S1 platform for hardware regressions and software development at much higher speed than emulation, which enables us to focus the Palladium Z1 platform on high-value use models in the hardware and software verification domain.”

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80% re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

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