Design

Prototyping platform accelerates HW/SW integration process

2nd May 2017
Alice Matthews


In order to deliver multimedia System-on-Chip (SoC) designs to market faster, Amlogic has adopted Cadence Design Systems' new Cadence Protium S1 FPGA based prototyping platform. Using the Protium S1 platform, Amlogic accelerated its hardware/software (HW/SW) integration process, resulting in a time savings of two months compared to its previous traditional HW/SW integration method. 

Amlogic, an early participant in the Protium S1 platform beta programme, found that the platform’s implementation and accelerated time to prototype capabilities enabled its engineering team to begin software development on its SoC designs earlier than before. The platform also allowed designers to boot Linux and Android faster and run AnTuTu benchmark scoring in a single day.

“The Protium S1 platform enabled us to successfully run multiple instances of the design in parallel so that we could be much more productive,” said Jerry Cao, Software Engineering Director at Amlogic. “In addition, the platform shares a common compile flow with the Cadence Palladium Z1 Enterprise Emulation Platform, which allows us to re-use our existing Cadence verification environment and achieve functional congruency between the two platforms.”

The company claims that the Protium S1 FPGA-based prototyping platform is a next-gen platform that enables early software development, reducing design bring-up time by an average of 80% versus traditional FPGA prototyping approaches. The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

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