Design

PCI Express 5.0 IP interoperability with xeon scalable processor

15th October 2020
Alex Lynn

Synopsys has announced its collaboration with Intel to achieve successful system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids).

The full-system interoperability, a key milestone in Synopsys and Intel's ongoing collaboration, enables the ecosystem to confidently use the companies' proven technologies to accelerate development of their PCIe 5.0-based products in high-performance computing and AI applications.

The DesignWare IP for PCI Express 5.0 has been licensed over a hundred times by customers across all key market segments, delivering the lowest latency and highest throughput IP compared to other solutions in the industry.

"Synopsys continues to collaborate with industry leaders like Intel to deliver high-quality IP that help designers address the bandwidth, power, area, and latency demands for the new era of high-performance computing systems," said John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys. "Achieving successful interoperability between Synopsys' DesignWare IP for PCIe 5.0 and Intel Xeon Scalable processors validates that the IP functions as intended with Intel's industry-standard PCIe 5.0 products, accelerating the path to first-silicon success with less risk."

"The growth of high-performance computing applications converged with AI workloads requires innovative data connectivity and processing technologies that deliver low latency and fast speeds," added Jim Pappas, Director of Technology Initiatives at Intel. "We are pleased to collaborate with Synopsys, a leading provider of PCIe IP, to enable the ecosystem and ensure the widely adopted DesignWare IP for PCI Express 5.0 is interoperable with our future CPUs in order to enable the billions of PCIe-enabled products in the market."

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