Design

mimoOn and Tektelic Introduce LTE Small Cell Reference Design

• Design

3 June 2013

byNews Desk

Synopsys Delivers Comprehensive Design Implementation Solution for Samsung’s Leading-Edge 14-Nanometer FinFET Process

• Design

3 June 2013

byNews Desk

Cavium Launches New Production Ready Small Cell Reference Design with Support for Dual Radio Access Technology

• Design

3 June 2013

byNews Desk

Embedding Natural User Interfaces

• Design

3 June 2013

byNews Desk

Building New Bridges

• Design

3 June 2013

byNews Desk

PMC Adopts Cadence Physical Verification System as Signoff Technology for Large Complex SoC

• Design

3 June 2013

byNews Desk

3L ports 3L Diamond multiprocessing software tools to CommAgility DSP board making multicore development easy to harness performance

• Design

3 June 2013

byNews Desk

Microsemi Adopts Cortus Processor Core For Mixed Signal SoC Platform

• Design

3 June 2013

byNews Desk

ARM Expand Partnership With Carbon Design Systems

• Design

3 June 2013

byNews Desk

Mentor Graphics and Samsung Optimize 14nm Process Design Kits

• Design

3 June 2013

byNews Desk

ProximusDA teams with STMicroelectronics to Develop Next-generation Distributed SOC TLM Virtual Prototypes

• Design

31 May 2013

byNews Desk

Supermicro Announces X10 Server Building Blocks Supporting Intel Haswell Processors

• Design

31 May 2013

byNews Desk

Mentor Graphics and GLOBALFOUNDRIES Deliver 20nm Design Kits for Advanced Design Enablement

• Design

31 May 2013

byNews Desk

CaetanoBus Streamlines its Electrical Design Processes Using Capital Software from Mentor Graphics

• Design

30 May 2013

byNews Desk

LDRA–Lauterbach integration delivers complete code coverage, test case verification and certification compliance for broad range of applications and platforms

• Design

30 May 2013

byNews Desk

Cadence Design Tools Certified for TSMC 16nm FinFET Process and for TSMC 20nm Process

• Design

30 May 2013

byNews Desk

Agilent Technologies Introduces Electrical Retimer Solution to Solve Key Challenges in Designing Chip-to-Chip Links

• Design

30 May 2013

byNews Desk

AdaCore Announces Successful Completion of Project Hi-Lite

• Design

30 May 2013

byNews Desk

TSMC Certifies Synopsys’ Digital and Custom Solutions for 16-nm FinFET Process

• Design

29 May 2013

byNews Desk

Agilent Technologies’ Newest 3-D Electromagnetic Simulation Software Release Targets EMI Compliance

• Design

29 May 2013

byNews Desk