Oasys Design Systems Adds SystemVerilog Support To RealTime Designer

“We are pleased and proud to have added System Verilog support within one year of delivering VHDL,” states Paul van Besouw, Oasys’ president and chief executive officer. “Design teams employing RealTime Designer are at the cutting edge of design and are increasingly using System Verilog.”

Support for SystemVerilog comes standard with RealTime Designer and is available immediately. In addition to SystemVerilog, RealTime Designer accepts Verilog and VHDL input, along with standard timing and physical libraries, SDC timing constraints and floorplans.

Chip Synthesis is a fundamental shift in how synthesis is applied to the design and implementation of integrated circuits (ICs). RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. It features a unique RTL code placement approach that eliminates unending design closure and iterations between synthesis and layout.

RealTime Designer follows a “Place First” methodology that takes RTL code, partitions it into blocks, places the RTL code in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement it until chip-level constraints are met.