New Release of Lattice Diamond Design Software Delivers More Rubust Design Capabilities for Low Power, Cost Sensitive FPGA Applications
Lattice Semiconductor Corporation has announced release 1.3 of its Lattice Diamond design software, the flagship design environment for Lattice FPGA products. Users of Lattice Diamond 1.3 software will benefit from major new features, including clock jitter analysis. Lattice Diamond 1.3 software is also now integrated with Lattice’s PAC-Designer 6.1 mixed signal design tools (also announced today), providing design support for Lattice’s programmable mixed signal Platform Manager devices.In a
“Our users are migrating quickly to Lattice Diamond design tools in order to benefit from the intuitive design environment and high quality of results required for low power and cost sensitive FPGA applications,” said Mike Kendrick, Lattice’s Director of Software Marketing.
“Lattice Diamond 1.3 software further extends the user productivity and quality of results they have come to expect from Lattice Diamond design tools.”
Enhanced Support for the MachXO2 Device Family
The Lattice Diamond design environment enables users to easily explore design alternatives as they target cost sensitive, low power, high volume applications – the type of applications ideally suited for the MachXO2 family. Lattice Diamond 1.3 software now includes updated timing and power analysis device information, as well as final production package, bit stream and SSO analysis data based on the actual silicon characterization for the MachXO2 LCMXO2-1200 and LCMXO2-1200U devices. Notably, these changes, plus ongoing improvements to the synthesis, MAP and PAR implementation engines, have resulted in an FMax improvement of 5% to 15% on most designs targeted to the LCMXO2 devices.
More Robust Design and Optimized Cost In Less Time
Lattice Diamond 1.3 software enables users to design with more confidence and ensures designs are more robust and resilient to their operating environment. For example, designers can now add user-defined clock jitter to their design’s clocks while they are performing static timing analysis of these designs. Users control the amount of clock jitter they want to model on the clock signal through an extension to the existing timing preferences, and see the analysis results in both the Trace report and the Timing Analysis view. The Timing Analysis view rapidly updates the analysis results when the clock jitter is changed.
In addition, Lattice Diamond 1.3 software now aids users who want to migrate their designs to a lower cost device within the same device family while preserving the current package and board layout. This capability is available for both the MachXO2 device family and the higher performance LatticeECP3™ FPGA devices. Users are provided pin migration information in the Package view and Spreadsheet views, such as incompatible pins. This pin migration information can also be exported to the Pin Layout file.
More Efficient Design Flow
Lattice Diamond software incorporates an intuitive, modern GUI that enables several new concepts that help users quickly explore design alternatives to meet their cost, power and performance goals. Lattice Diamond 1.3 software extends this approach with several new design flow enhancements. For example, projects can now support complex multi-file testbenches and allow multiple design representations for the same design block (such as one description for synthesis and a different description for simulation). The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator. In addition, the synthesis design constraints flow is now more intuitive and allows for multiple files that can be managed similar to the back-end preference files. And, when using the Reveal™ Analyzer, Lattice Diamond’s on-chip debugger, users can now download large trace data amounts and configure complex trigger setups more than 10 times faster than previously possible.
Design Exploration Made Easy
Lattice Diamond 1.3 software now provides device resource utilization for each logical level of the design hierarchy following synthesis, and enables users to make early design decisions about how to structure their design so that they can optimize utilization of the overall device.
Also, in order to explore design alternatives, users can now select the best run when using parallel processing of the multiple implementations provided by Run Manager. Users can now directly select the active implementation in Run Manager and also control which one of the multi-par runs is used so that the rest of the design flow can be focused on the implementation that provides the best placement and routing run for that design.
Improved Ease of Use
The Lattice Diamond user interface combines leading edge features and customization with improved ease of use so users can complete their design more quickly. With Lattice Diamond 1.3 software, users can now program their devices in a very intuitive fashion. The new Diamond Programmer fully supports the direct programming features of the ispVM™ System, a comprehensive stand-alone device programming manager. Diamond Programmer significantly improves the ease of use of the most common steps such as setting up the cable, scanning the board, and direct programming of the device. Diamond Programmer is available either fully integrated into the Lattice Diamond environment or as a standalone tool.
Integration with PAC-Designer 6.1 Software
Lattice Diamond 1.3 software provides an automated simulation environment not previously available to mixed signal designers, and integrates with PAC-Designer 6.1 software to simplify platform management design. Whether testing the functionality of critical analog I/O pin functions controlled by the Platform Manager’s internal CPLD, or checking the integration of enhanced digital control functions coded in Verilog or VHDL within the Platform Manager’s FPGA control section, PAC-Designer 6.1 software integrates seamlessly with Lattice Diamond 1.3 design tools to compile the entire design, create the necessary stimulus file and then automatically generate initial timing waveforms within the Aldec Active-HDL Simulator.
Third Party Tool Support
Lattice Diamond software incorporates Synopsys’ Synplify Pro advanced FPGA synthesis for Windows and Linux. Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows.
In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also available in the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
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