New algorithms added to DesignWare security protocol
Synopsys has announced that it has added the ChaCha20 and Poly1305 (RFC7539) algorithms to its DesignWare Multipurpose Security Protocol Accelerator IP, enabling designers to efficiently implement the latest encryption and authentication functionality to protect their IoT SoCs. The Security Protocol Accelerator IP increases security protocol performance by supporting efficient data sequencing as well as parallel processing of cryptographic operations such as authentication and encryption/decryption.
With the addition of these algorithms to the Security Protocol Accelerator IP, designers can secure Internet communication applications that rely on the Transport Layer Security (TLS) protocol version 1.2 and 1.3, including browsers, voice-over-IP devices, and smart home applications.
The DesignWare Multipurpose Security Protocol Accelerator IP accelerates a broad range of computationally intensive cryptographic algorithms as required by most security protocols, such as SSL/TLS, IPsec, WiFi and LTE. The Security Protocol Accelerator IP's advanced security features include Trusted Execution Environment (TEE) support, secure key access and differential power analysis countermeasures to increase protection against threats.
The virtualisation feature allows designers to share a single Security Protocol Accelerator instance across multiple host processors, or a multi-core processor, to offload security functionality for reduced gate count, small memory footprint, and simplified software management.
"SoC designers rely on security protocol accelerators to increase performance and reduce latency of cryptographic algorithms in SoCs," said John Koeter, Vice President of Marketing for IP at Synopsys. "The addition of the ChaCha20 and Poly1305 algorithms as well as side-channel countermeasures to the DesignWare Security Protocol Accelerator IP enables more secure Internet communication for millions of connected devices that rely on the TLS protocol."