Design

Network synchroniser clock with two frequency domains

25th March 2019
Alex Lynn

The LMK05318 from Texas Instruments is a high-performance network synchroniser clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications.

The ultralow jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links. The device can generate output clocks with 50-fs RMS jitter using TI's proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

The DPLL supports programmable loop bandwidth for jitter and wander attenuation, while the two APLLs support fractional frequency translation for flexible clock generation. The synchronisation options supported on the DPLL include hitless switching with phase cancellation, digital holdover, and DCO mode with less than 0.001-ppb (part per billion) frequency step size for precision clock steering (IEEE 1588 PTP slave).

The DPLL can phase-lock to a 1-PPS (pulse-per-second) reference input and support optional zero-delay mode on one output to achieve deterministic input-to-output phase alignment with programmable offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimise output clock disturbance when a loss of reference (LOR) occurs.

To view the full datasheet, click here.

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