Multichannel RF transceiver clocking reference design

15th May 2019
Alex Lynn

Analogue front end for high-speed end equipment like phased-array radars, wireless communication testers, and electronic warfare require synchronised, multiple transceiver signal chains. Each transceiver signal chain includes high-speed, analogue-to-digital converters (ADCs), digital-to-analogue converters (DACs), and a clock subsystem. 

The clock subsystem provides low noise sampling clocks with precise delay adjustment to achieve lowest channel-to-channel skew and optimum system performance like signal-to-noise ratio (SNR), spurious free dynamic range (SFDR), IMD3, effective number of bits (ENOB), and so forth. 

This reference design demonstrates multichannel JESD204B clocks generation and system performance with AFE7444 EVMs.

Channel-to-channel skew better than 10ps achieved with six GSPS/3 GSPS DAC/ADC clocks up to 2.6GHz radio frequencies and system performance like SNR and SFDR are comparable to the AFE7444 data sheet specifications. 

To learn more, click here.

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