Multi-channel JESD204B 15GHz clocking reference design
High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design from Texas Instruments (TI) is capable of supporting two high speed channels on separate boards.
It does this by utilising TI’s LMX2594 wideband PLL with integrated VCOs to generate a ten megahertz to 15GHz clock and SYSREF for JESD204B interfaces. The ten kilohertz offset phase noise is < -104 dBc/Hz for a 15GHz clock frequency.
By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25GHz input signal. All key design theories are described, guiding users through the part selection process and design optimisation. Finally, schematic, board layout, hardware testing, and results are also presented.
Features
- Up to 15GHz sample clock generation.
- Multi-channel JESD204B compliant clock solution.
- Low phase noise clocking for RF sampling ADC/DAC.
- Configurable phase synchronisation to achieve low skew in multi-channel system.
- Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57).
To find out more, click here.
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