Mentor Graphics Tessent YieldInsight Demonstrates Faster IC Failure and Yield Analysis at Fujitsu

The Tessent YieldInsight tool can help accelerate customers’ ramp to production volume, quickly resolve yield excursions, and improve their mature yield, leading to increased profitability, lower defects-per-million (DPM) rates, and higher customer satisfaction.

According to Takahiro Fujimi, Manager of the Product Engineering Department, Product Technology Division, Fujitsu Semiconductor Limited, “We evaluated Mentor’s yield analysis technology on a 15 million gate design manufactured on a 65 nm process. When used together with Mentor’s Tessent TestKompress® ATPG product, we found Tessent YieldInsight to be very effective in quickly and accurately identifying the actual physical locations of many IC failures. The product’s intuitive graphical interface is consistent with traditional yield analysis techniques and enables product engineers to be more effective in identifying yield problems and determining the cause of systematic defects.”

“Tessent YieldInsight is exciting new technology because it addresses time-to-market and manufacturing cost issues, both critical factors in the profitability of IC products,” said Joseph Sawicki, Vice President and General Manager of Mentor’s Design to Silicon division. “Customers can use the product to easily resolve problems with ramping production volume for new products, and they can use it to maximize mature product yield. Tessent YieldInsight represents an innovative new use of test data that already exists in our customers’ production flows.”