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Mentor Graphics Teams with TSMC to Enrich Reference Flow 11 Low Power Verification Solutions

28th March 2011

ES Admin

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Mentor Graphics announced it has expanded the use of low power verification capabilities in TSMC’s Reference Flow 11 to address today’s complex integrated circuit (IC) low power functional verification requirements. The Mentor® low power verification tool suite includes the Questa® functional verification platform, the 0-In® CDC (Clock Domain Crossing) and the 0-In Formal tools and the FormalPro™ equivalence checking tool.

“Many design teams struggle with the functional verification of their designs where low power requirements put increased pressure to meet functional specifications,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “Mentor continues to show a high degree of commitment to enhance the capabilities of their functional verification technologies, and considerable foresight to determine what new capabilities will be required in the years to come.”

“Low power requirements are a top priority for a majority of our mutual customers,” said John Lenyo, general manager, Mentor Graphics. “That’s why effective low power design verification solutions continue to be one of our top priorities, and we intend to extend our collaboration with TSMC on future reference flow programs.”