Lattice Announces Update, More Accessible CPLD Design Tools

3rd August 2009

ES Admin

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Lattice Semiconductor has announced the immediate availability of Version 1.3 of its ispLEVER Classic design tool suite. Version 1.3 includes updated support for Lattice CPLDs (Complex Programmable Logic Devices), including the widely popular ispMACH 4000 device family. Designers can quickly download, for free, ispLEVER Classic for Windows, as well as optional Synopsys Synplify logic synthesis and Aldec Active-HDL simulator modules from: www.latticesemi.com/products/designsoftware/isplever/ispleverclassic. The ispLEVER Classic software download has been segmented into modules to make download and installation faster and more convenient.

The ispLEVER Classic 1.3 software also includes updated ordering part number designations for GAL 22V10 lead free QFNS package devices. To further support designers who maintain mature systems with discontinued Lattice devices, ispLEVER Classic1.3 software now includes the Obsolete Pack, which enables additional device support within the design tools. To enable the pack, users simply check the Show Obsolete Devices option within the new Project Wizard feature of the Project Navigator application.

ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products. It can be used to take a Lattice device design completely through the design process, from concept to device JEDEC or bitstream programming file output.

In addition to the tool support for Lattice devices provided by the downloadable versions of Synopsys Synplify for Lattice and Active-HDL Lattice Web Edition, Lattice devices are also supported by the full versions of Synopsys Synplify and Aldec Active-HDL.