ITRI Tapes Out 3D-IC Chip Using Cadence Technology

The 3D-IC approach—in which multiple ICs are stacked in a single package—is becoming increasingly necessary to meet the size, cost, power, and performance demands for advanced electronics.

“We have been collaborating closely with Cadence for more than a year, using its end-to-end 3D-IC flow to address the challenges in designing with stacked dies and TSVs,” said Dr. Cheng-Wen Wu, general director of Information and Communications Research Laboratories (ICL) and vice president at ITRI. “As a result of the deep collaboration, we now have successfully taped out our first 3D-IC chip. We look forward to continuing our leading work with Cadence in this rapidly emerging area.”

Cadence technologies deployed include Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Test, Encounter Timing System, Encounter Power System, the Cadence Physical Verification System, and QRC Extraction.

“Cadence is working with advanced customers to address emerging technology challenges like 3D-IC design, offering a uniquely deep set of integrated technologies that span custom/analog, digital, design for test, and package environments,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “We recognize the benefits the industry receives from leading research organizations like ITRI that are working to help bring the benefits of 3D-IC design to the semiconductor industry faster.”