IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.
The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pin device in half an hour.
What is new in IO Checker 2.2
New functionality includes an alternate device, where IO Checker can now verify the connectivity for a second (migration) device. The device view shows information for the alternate device in the bottom right corner of each pin. Verification will report issues like pins not connected on the alternate device, or user IO pins that promote to power or ground.
Other improvements are in power and ground verification, PCB net type icon indication, improved search widgets. Xilinx Vivado tool support has been added. More information about new functionality can be found on the company website.
Device Support
Support has been added for the Altera Cyclone V / Stratix V and Xilinx Artix 7 / Kintex 7 / Virtex 7 / Zynq devices.
Availability and Pricing
IO Checker 2.2 is available now. Prices begin at € 750 or US$1,125. IO Checker can be downloaded and evaluated by qualified FPGA and PCB designers.