Nitero selected Synopsys because of its high-quality, small area and low-power IP, as well as for its industry-leading design tools. These tools include the Design Compiler RTL synthesis solution with power optimisation and PrimeTime timing and power analysis tool, two key components of the Galaxy Design Platform.
“Developing a low-power mobile SoC that incorporates both analogue/mixed-signal IP and RF technology was challenging, so we needed IP and tools that were proven to work the first time,” said Sebastian Ahmed, Vice President of Engineering, Nitero. “After evaluating several vendors, we selected Synopsys DesignWare IP, Verification IP and Galaxy Design Platform as it provided a seamless, end-to-end design experience, helping us meet our aggressive tapeout schedule and achieve first-silicon success.”
“Designers rely on Synopsys to provide high-quality IP and tools that will help them mitigate risk and deliver successful products to the market on schedule,” said John Koeter, Vice President of Marketing for IP and prototyping, Synopsys. “As a leading provider of tools and IP, with more than 1,000 PCI Express design wins, Synopsys enables companies like Nitero to gain a competitive edge and focus engineering resources on differentiating portions of its designs.”
The DesignWare Controller IP for PCI Express technology is silicon-proven and available now. Synopsys’ Verification IP, Design Compiler and PrimeTime are also available now.
