Design

IC design flow certfied for Samsung's 3nm GAA process

29th October 2020
Mick Elliott

Cadence Design Systems says that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 3nm GAA process technology for early design starts.

The certification ensures mutual customers of Cadence and Samsung Foundry have immediate access to a highly automated circuit design, layout, signoff and verification flow to efficiently design products for automotive, mobile, data center, artificial intelligence (AI) and other emerging applications at 3nm.

The automated Cadence custom and AMS full flow supports the company’s Intelligent System Design strategy, enabling SoC design excellence.

When designing for the 3nm GAA process, the Cadence Virtuoso layout flow provides a high level of automation and integration, enabling faster design closure with reduced numbers of iterations.

The Cadence tools in the flow incorporate key features that are well suited for digitally assisted analog designs such as high performance, best-in-class analysis and verification capabilities developed in the Cadence Spectre Accelerated Parallel Simulator (APS). In addition, the Innovus Implementation System and the Cadence digital suite are enabled for the Samsung 3nm process node, allowing customers to implement larger, more complex digital blocks.

The complete, certified custom and AMS flow includes the VirtuosoADE Suite, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Layout Suite Electrically Aware Design (EAD), Spectre X Simulator, Voltus-Fi Custom Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyser (LPA), LDE Electrical Analyser (LEA), Innovus Implementation System, and Pegasus Verification System. Key technical capabilities include: 

  • Schematic migration: Allows automated migration using the Cadence Virtuoso Automated Layout Enhancer framework
  • Circuit design and verification: Lets users verify circuit performance and reliability by performing static and dynamic circuit checks, DC/TRAN/C/STB corner simulation, transient noise simulation, Monte Carlo simulation and high-yield estimation, periodic steady state (PSS), periodic small-signal (PNOISE), ageing and IR drop and electromigration (EM-IR) analysis
  • Analogue layout: Providesimproved productivity viaautomated constraint-driven, row-based device placement and routing with support for width spacing patterns (WSPs), automated routing with WSPs and pin-to-trunk features, EAD to achieve electrically correct designs with reduced iterations, DRC verification during layout using the signoff deck and the Pegasus Verification System’s interactive capabilities, and automated digital block implementation
  • Physical verification and signoff: Offers post-layout simulation in Spectre X Simulator using Quantus extracted parasitics in detailed standard parasitic format (DSPF), full-chip DRC, layout versus schematic (LVS) signoff and color decomposition using Pegasus verification, and DFM pattern matching check using LPA for detecting and correcting process hot spots and improving yields
  • Custom digital and P&R digital layout: Enables seamless interoperability between the Virtuoso platform and Innovus Implementation because the process design kit (PDK) techfile is mixed-signal OpenAccess-ready. For digital block implementation using custom digital methodology, after power mesh using WSP Power Routing (WPR) in the Virtuoso platform and automated row-based standard cell placement using the Virtuoso custom placer, the design is taken into Innovus Implementation for digital routing. The pure digital block can be entirely implemented in Innovus Implementation and brought back into the Virtuoso platform for integration.

“We have validated the Cadence AMS tools along with the entire flow, and it meets our requirements for designing with 3nm GAA process technology,” said Sangyun Kim, Vice President of Foundry Design Technology Team at Samsung Electronics. “This high-performance flow is available immediately to our customers and represents a major milestone in our ongoing collaboration with Cadence. This additional step provides our customers with advanced design capabilities to improve productivity and fulfill market challenges.”

“In collaboration with Samsung, we’ve achieved certification for our integrated AMS flow at 3nm GAA to drive continued advancements with next-generation design work,” commented KT Moore, vice president, product management in the Custom IC and PCB Group at Cadence. “Based on our leading Virtuoso and Spectre platforms, the flow enables highly efficient AMS designs so our mutual customers can quickly complete complex 3nm designs to meet the needs of evolving end-markets, including automotive, AI, and 5G.”

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