Solido announces High-Sigma Monte Carlo meta-simulator

Solido’s High-Sigma Monte Carlo meta-simulator provides rapid analysis of yield/performance trade-offs for memory design. It achieves high-sigma memory verification in thousands rather than millions or billions of simulations. It analyzes the billions of Monte Carlo samples, and then focuses its SPICE simulation resources to find rare failures or validating the target yield. It also runs fast enough to facilitate both iterative design and verification within production timelines. A Solido HSMC 5 billion Monte Carlo sample run can take as little as 15 minutes.

Solido’s HSMC provides SPICE-accurate information in the extreme tails of the high-sigma distribution, where defects are expected to occur and is applicable to production-scale high-sigma designs with hundreds of process variables. It interfaces to all the leading SPICE simulators used by memory designers and runs at the command-line, just like a single simulation, while supporting parallelization to hundreds of cores/machines and managing multiple simulations through LSF/SGE. It analyzes design sensitivities to variation, presenting design opportunities to shrink memory area, power and improve performance, as well as providing integrated results verification.

“With increasing pressure for high yield and performance designs, designers are faced with a daunting level of analysis to understand the impact of variation on their designs,” said Amit Gupta, President and CEO of Solido Design. “Solido’s High-Sigma Monte Carlo meta-simulator is already being successfully deployed at several companies because alternate methods are too slow, insufficiently inaccurate, and do not scale across the range of circuits memory designers need to analyze.”

Driven by the higher level of integration demanded for mobile devices, memory IP is an integral part of SoC design, and requires low power, minimum cost and die area, and maximum performance at high yield. As a result, memory designers are early adopters of state-of-the-art foundry processes (28nm and below). The increased variability associated with these new processes leads to increased risks in yield while meeting aggressive power, performance and area goals.

Many memory elements, such as bit cells and sense amps, are replicated in large arrays so that producing a single working product requires that the millions of repeated cells all work correctly, without failure. This makes high yield design a requirement; by definition, 5-sigma has only one failure in two million, and 6-sigma has only one failure in a billion. The number of simulations required to validate high yield using traditional methods is simply infeasible, even with today’s fastest simulators, and even while utilizing massive compute clusters and cloud computing.

There is a continuing progression of electronic design automation tools to manage increased complexity through greater abstraction and partitioning methods. Meta-simulators are part of this trend. A meta-simulator feels like using a single simulator to the designer, yet drives hundreds or thousands of simulations in parallel from traditional simulation engines. Meta-simulators offer a “meta-level” analysis that may utilize a large number of simulations, while keeping the user input to not much more than a netlist. The output is simple, numerical, and well-defined, just like the result of a simulation.

Meta-simulation has historically been limited to simplistic methods, such as running corners or running Monte Carlo. Today, meta-simulation techniques can be much more powerful, addressing designer challenges and speeding up different analyses types in precisely-targeted ways. For example, rather than running 100 or 10,000 PVT corners just to search for the worst cases, a “Fast PVT” meta-simulator would analyze all the PVT corners and intelligently simulate only the small subset requires to identify the worst-case corners with confidence.

Meta-simulation goes beyond distributed processing; it also adds efficiency to high-value analysis capabilities such as: fast PVT analysis; fast extraction of statistical corners; and fast sensitivity analysis. An ideal meta-simulator for memory design measures yield-performance tradeoffs out to 5 and 6-sigma, with the same accuracy as millions or billions of Monte Carlo simulations, but with 100x+ fewer simulations.