Helping designers to manage complexity

To address the challenges that come with advanced node FinFET designs, capabilities in the Cadence Virtuoso Advanced-Node Platform allow designers to better manage complexity and process effects. The key capabilities include:

Multi-patterning and colour aware layout: Supports more than four multi-patterned layers for design decomposition, enabling users to be far more productive through access to a variety of colouring options.

Electrically aware design (EAD): Allows designers to address parasitic and electro-migration (EM) effects during the design cycle versus waiting until designs are completed, thereby reducing design cycle times by up to 30%.

Module generator (ModGen)-based device array flow: Provides support for in-array routing, greatly reducing design iterations and improving designer productivity by up to 25X.

10nm custom routing: Supports new design rules, greatly simplifies layout creation and minimises colouring errors that can be pervasive when designing on the 10nm process.

In-design physical verification system (iPVS): Enables layout engineers to instantaneously detect and fix errors as designs are being implemented, which can greatly reduce design rule errors while improving overall designer productivity by up to 15%.

“Innovation is the core of our business, and through our close collaboration with leading foundries and customers, we’ve been able to optimise our custom design platform for advanced-node processes,” said Tom Beckley, Senior Vice President and General Manager, Custom IC and PCB Group at Cadence. “The new features included with the Virtuoso Advanced-Node Platform can enable our customers to achieve the best possible results, and we already have several customers using it in production design starts to reduce the overhead inherent with 10nm designs.”