Green Hills Software supports NXP i.MX 8 processors
Green Hills Software has announced that its INTEGRITY-178 Time-Variant Unified Multi-Processing (tuMP) RTOS now supports heterogeneous multicore operation on NXP Semiconductor’s i.MX 8 processors across Arm Cortex-A72 and Cortex-A53 cores for airborne safety-critical and security-critical systems.
Using the bound multi-processing (BMP) and symmetric multi-processing (SMP) capabilities in INTEGRITY-178 tuMP, a system architect can assign an application to a particular core or a multi-threaded application to execute across multiple cores of a particular type to maximise multicore utilisation while minimising power consumption.
“NXP Semiconductors is committed to providing multicore processors with advanced features to meet the needs of avionics applications,” said Jeff Steinheider, Director, Global Industrial Applications Processor Product Marketing for NXP Semiconductors. “The unique multi-processing capabilities built into the INTEGRITY-178 tuMP RTOS make it ideal for exploiting the heterogeneous processing of the i.MX 8 applications processor in airborne safety- and security-critical systems.”
NXP i.MX 8 applications processors have several features that are useful for avionics, airborne mission computers, and cockpit displays, including SWaP-optimised heterogeneous processing, quad-display functionality, low soft-error rate, and product supply longevity. With four Cortex-A53 cores and two Cortex-A72 cores, the i.MX 8QuadMax enables power consumption optimisation by matching the performance requirements of each application task to the performance capacities of the different cores.
For cockpit displays and other graphics applications, the processor can drive up to four 1080p screens with independent content. The low soft-error rate of i.MX 8 processors results from a robust 28 nm FDSOI manufacturing process, which has inherently high immunity to alpha particle flux and enables high MTBF. Along with many of NXP’s product families, the i.MX 8 processors have a minimum of 10-15 years of product supply longevity.
Certifying multicore processors for airborne safety can be quite challenging due to the inherent contention from multiple cores trying to access a given shared resource, such as memory or I/O. INTEGRITY-178 tuMP includes both a fully capable multicore scheduler and support for bandwidth allocation and management of shared processor resource access.
The supported bandwidth management technique emulates a high-rate hardware-based approach to ensure continuous allocation enforcement. These capabilities greatly lower integration and certification risks while also enabling integrators to gain the maximum performance advantages of multicore processors.
The INTEGRITY-178 tuMP safety- and security-critical RTOS is designed to simultaneously meet DO-178B/C design assurance level (DAL) A and the separation kernel protection profile (SKPP) as defined by the NSA. INTEGRITY-178 tuMP is a multicore RTOS with support for any mixture of asymmetric multi-processing (AMP), SMP, and BMP. Specifically, it includes support for running a multi-threaded DO-178C DAL A partition across multiple processor cores in SMP or BMP configurations as required in ARINC 653 Part 1, Supplements 4 and 5.
INTEGRITY-178 tuMP was the first RTOS to be certified conformant to the FACE Technical Standard, edition 3.0, and remains the only one conformant for all three avionics processor architectures: Arm, Intel, and Power Architecture.