Flexible 3.2-GSPS multi-channel AFE reference design for DSOs

This high speed multi-channel data capture reference design from Texas Instruments enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and deterministic latency.

This reference design demonstrates multi-channel AFE and clock solution using high speed data converters with JESD204B, high speed amplifiers, high performance clocks and low noise power solutions to achieve optimum system performance.

To learn more, click here.

Keep Up to Date with the Most Important News

By pressing the Subscribe button, you confirm that you have read and are agreeing to our Privacy Policy and Terms of Use
Previous Post

Toughened epoxy polysulfide hybrid offers chemical resistance

Next Post

Dual isolated output bias power supply with low standby consumption