Finding developers the freedom to innovate in low-power
By unveiling the architecture for a new class of SoC FPGAs at the RISC-V Summit, Microchip, via its Microsemi Corporation subsidiary, announced an extension to its Mi-V ecosystem. The new family combines the industry’s lowest power mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V Instruction Set Architecture (ISA).
Announced at the RISC-V Summit in Santa Clara, California, Microchip’s new PolarFire SoC architecture brings real-time deterministic Asymmetric Multiprocessing (AMP) capability to Linux platforms in a multi-core coherent Central Processing Unit (CPU) cluster.
The PolarFire SoC architecture, developed in collaboration with SiFive, features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory. This allows designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal- and space-constrained applications in collaborative, networked IoT systems.
In a new era of computing driven by the convergence of 5G, machine learning and the Internet of Things (IoT), embedded developers need the richness of Linux-based operating systems. These must meet deterministic system requirements in ever lower power, thermally-constrained design environments, while addressing critical security and reliability requirements.
Traditional System-On-Chip (SoC) Field Programmable Gate Arrays (FPGAs) blend reconfigurable hardware with Linux-capable processing on a single chip to provide developers with ideal devices for customisation, yet consume too much power, lack proven levels of security and reliability, or use inflexible and expensive processing architectures.
PolarFire SoC includes extensive debug capabilities including instruction trace, 50 breakpoints, passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors and FPGA fabric monitors, in addition to Microchip’s built-in two-channel logic analyser, SmartDebug.
The PolarFire SoC architecture includes reliability and security features such as Single Error Correction and Double Error Detection (SEC-DED) on all memories, physical memory protection, a Differential Power Analysis (DPA) safe crypto core, defence-grade secure boot and 128Kb Flash boot Memory.
Evaluation and design with PolarFire SoC are supported by the antmicro Renode system modelling platform, which is now integrated with Microchip’s SoftConsole Integrated Design Environment (IDE) for embedded designs targeting PolarFire SoCs. A PolarFire SoC development kit is also available now, consisting of the PolarFire FPGA-enabled HiFive Unleashed Expansion Board and SiFive’s HiFive Unleashed Development Board with its RISC-V microprocessor subsystem.
Microchip is also launching a new Mi-V Embedded Experts Program, a worldwide partner network to assist customers in hardware/software designs for PolarFire SoC. The addition of this programme ensures support throughout the entire lifecycle of customer products and helps to jump-start designs and shorten time to market. Members also get access to direct technical support and early access to development platforms and silicon.