Design

DisplayPort 2.0 Verification IP accelerates SoC designs

28th June 2019
Mick Elliott

Availability of a Verification IP (VIP) in support of the new DisplayPort 2.0 standard has been announced by Cadence Design Systems. The Cadence VIP for DisplayPort 2.0 enables designers to quickly complete the functional verification of their mobile, Audio-Visual and AR/VR system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.

The VIP for DisplayPort 2.0 has been architected to meet the specifications of the new standard—enhancing design verification productivity, ensuring high-quality designs and delivering maximum performance.

It offers a comprehensive protocol validation solution for DisplayPort designs and includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimise verification predictability.

Additionally, the VIP has been designed for easy integration into testbenches at IP, SoC and system levels, helping engineers reduce time to first test and accelerate verification closure.

Maurizio Paganini, EVP and COO at MegaChips, a fabless semiconductor company in Japan, and a leading developer of semiconductors with expertise in analogue, digital and MEMS technology, said: “Our team has successfully utilised the Cadence VIP for DisplayPort for previous versions of the specification, which enabled us to deliver advanced audio and video IP solutions for personal computing, mobile and consumer AV devices. We are happy to see Cadence deliver VIP for the DisplayPort 2.0 specification. The DisplayPort 2.0 specification will be supported in our next generation of products for mobile computing, enterprise connectivity, gaming, AR/VR and AV streaming systems.”

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