Design

Digital full flow optimised to deliver improved quality

18th March 2020
Mick Elliott

The latest release of the Cadence digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimise power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and artificial intelligence (AI).

The flow features multiple industry-first capabilities including unified placement and physical optimization engines plus machine learning (ML) capabilities, enabling design excellence with up to 3X faster throughput and up to 20% improved PPA.

The new Cadence digital full flow delivers the PPA and throughput benefits through the following key enhancements:

  • Cadence digital full flow’s iSpatial technology: The iSpatial technology integrates the Innovus Implementation System’s GigaPlace Placement Engine and the GigaOpt Optimizer into the Genus Synthesis Solution, providing techniques such as layer assignment, useful clock skew and via pillars. The iSpatial technology allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database.
  • ML capabilities: ML capabilities enable users to leverage their existing designs to train the iSpatial optimization technology to minimize design margins versus traditional place and route flows.
  • Optimal signoff convergence: The digital full flow incorporates unified implementation, timing- and IR-signoff engines, offering enhanced signoff convergence by concurrently closing the design for all physical, timing and reliability targets. This allows customers to reduce design margins and iterations.

“The new digital full flow enhancements build upon the widely adopted integrated flow, further advancing Cadence’s digital and signoff design leadership position and enabling customers to achieve SoC design excellence,” Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We’ve collaborated closely with our customers who are under pressure to meet compressed schedules with increasingly large designs, offering them the features they need to realise PPA gains more efficiently.”

The Cadence digital full flow consists of the Innovus Implementation System, Genus Synthesis Solution, Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution. It provides customers with a fast path to design closure and better predictability and supports the company’s Intelligent System Design strategy, which enables advanced-node system-on-chip (SoC) design excellence.

“We spend a significant effort tuning our high-performance cores to meet our aggressive performance goals. Using the new ML capabilities in the Innovus Implementation System’s GigaOpt Optimizer, we were able to automatically and quickly train a model of our CPU core, which resulted in an improved maximum frequency along with an 80% reduction in total negative slack. This enabled 2X shorter turnaround time for final signoff design closure,” said Dr. SA Hwang, general manager of Computing and Artificial Intelligence Technology Group at MediaTek

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