Digital and signoff flow supports body-bias interpolation
Provider of system design tools, software, IP, and services, Cadence Design Systems, has announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for the GLOBALFOUNDRIES 22FDX process technology. The Cadence tools enable advanced-node customers across a variety of vertical markets - including automotive, mobile, IoT and consumer applications - to use GF’s fully depleted silicon-on-insulator (FD-SOI) architecture to optimise the power, performance and area (PPA).
To facilitate the adoption of GF’s 22FDX process technology, Cadence has enabled body-bias interpolation calculations in the following physical implementation and timing analysis tools:
- Innovus Implementation System: An advanced physical implementation tool, incorporating a massively parallel architecture that helps designers deliver high-quality SoCs in less time with PPA
- Tempus Timing Signoff Solution: A complete timing analysis tool that improves signoff timing closure via massively parallel processing and physically aware timing optimisation
In addition, Cadence and GF are actively working to enable the following solutions to support body bias interpolation on the 22FDX process:
- Genus Synthesis Solution: An RTL synthesis and physical synthesis engine that improves productivity challenges faced by RTL designers, delivering up to five times faster synthesis turnaround times
- Voltus IC Power Integrity Solution: A cell-level power integrity solution supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip SoC power signoff accuracy
Cadence and GF also collaborated on the delivery of a GF 22FDX digital reference flow and a downloadable process design kit (PDK) that incorporates the Cadence digital and signoff tools.
“Our collaboration with Cadence helps validate its digital and signoff flows that support FDX body-bias interpolation, which is a key differentiator with our FD-SOI process technologies,” said Jai Durgam, Vice President, Customer Design Enablement at GF. “This enablement within the Cadence tool suite allows our mutual customers to quickly and easily realise the performance, area and power benefits of 22FDX using body bias-interpolation techniques.”
“Through our support for body-bias interpolation, customers can confidently modify body-bias beyond the common usage of GF’s22FDX node to achieve optimal power and performance gains,” said KT Moore, Vice President, product management in the Digital & Signoff Group at Cadence. “Our efficient working model with GF helps customers implement designs quickly so they can remain competitive in their respective markets.”