“We have been working closely with Mentor to provide a comprehensive and consistent ecosystem for our customers,” said Kee Sup Kim, vice president of Infrastructure Design Center, Samsung Electronics. “We have used Mentor’s 32/28 nm DFM solution on several advanced SoCs to reduce late-stage problems that could lead to delayed product releases or slower than expected yield ramp-up. We are currently working with Mentor to expand the DFM solution to 20 nm processes as well.”
The components of the Calibre DFM platform at Samsung include the Calibre LFD™ product for litho simulation and hot spot pattern identification; the Calibre nmDRC and Calibre PM products for pattern-based design rule and hot spot checking and fixing; and the Calibre YieldAnalyzer product, which is used in conjunction with the Samsung manufacturing analysis deck for DFM scoring and critical area analysis (CAA).
“At advanced nodes, proper incorporation of DFM techniques can create a competitive edge for both foundries and fabless designers,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon Division at Mentor Graphics. “We are pleased to be working with Samsung on the Calibre platform to provide this competitive edge to our mutual customers.”