Board Designer Steps-up Electronic Product Design Quality

The latest chipsets with larger memories require designers to comply with an increasing set of design guidelines. For correct functional operation it is essential for signal skew to be able to match net lengths based on the defined constraints. With this in mind, as part of Zuken’s strategy to improve integration and deliver advanced functionality reuse across the CR-5000 environment, capabilities from its specialist high speed design and verification environment have been made available in Board Designer for the first stage of design and verification, including Embedded Intelligent Object functionality and various other utilities to facilitate with trunking and lengthening. By enabling more sophisticated routing to be completed earlier in the design cycle, design quality is greatly increased. Another advanced feature now incorporated specifically for designing with high pin count BGAs, is the support for vias in “Rules by Area”; plus enhanced wire length control with the ability to generate arc corners, used more and more to improve signal integrity.

Further functions have been added that aid in the process of editing designs, including extended list output for hole drawing with the addition of tolerances, comments and the ability to support customized list strings. It is also possible to edit prohibited layers and version 12.0 also enables the input of dimension lines to conform to the American Society of Mechanical Engineers standard, plus other generic editing function improvements such as the displaying of spread areas with tone patterns.

Forward annotation has also been enhanced for board generation making spacing rules easier to manage. This has been achieved by enabling users to import groups of spacing rules.

For efficient data exchange with mechanical CAD, the IDF/DXF interfaces now support default parameters and the IDF interface has added a feature for specifying input controls for component placement information, enabling MCAD to define board shapes and component positions automatically, early within the design process; minimizing errors and improving design quality.

There have been verification improvements for panel based design, with the introduction of layer consistency checks eliminating design errors, and verification and checking results can now be output into Excel formant to allow easy checking and investigation.

For increased precision in generating package data, the Ansoft interface now supports profile numbers in analysis when reviewing 3D shapes of bond wires, improving accuracy for package data. In addition, the cross probing functionality has been strengthened to aid efficiency and reduce design time.