CPU IP designed for safety critical systems
A highly-scalable 64-bit MIPS multiprocessing solution has been announced by Imagination Technologies that has been stringently assessed and validated to meet functional safety (FuSa) compliance for ISO 26262 and IEC 61508 standards. This makes it suitable for handling the compute-intensive tasks in emerging safety-critical systems such as autonomous vehicles, industrial IoT and robotics.
Surpassing the capabilities of other FuSa CPU IP cores, the I6500-F provides a high-performance, highly efficient backbone for the many-core designs that drive these systems, scaling to 64 heterogeneous clusters of multi-threaded multi-core MIPS CPUs and other accelerators in a system.
FuSa is essential to all parts of a safety-critical system, and that includes the CPU IP at the heart of the SoC. Applications such as autonomous vehicles and industrial control systems in smart factories require ever-increasing levels of processing that exceed the capabilities of today’s FuSa compliant CPU IP cores. Customers can use the extended performance capability of the I6500-F to efficiently integrate increased intelligence – including AI techniques such as CNNs and DNNs – in their safety-critical devices.
Jim Nicholas, EVP MIPS Processor IP, Imagination said: “We’re providing the performance needed to drive the compute-intensive tasks in a new generation of autonomous and intelligent systems. The I6500-F is a thoroughly tested IP solution that will help ensure customers can meet the most stringent safety requirements. If you are building an SoC for this kind of system today, you need the I6500-F.”
Driving advanced safety designs
Imagination is implementing fundamental safety technologies across the MIPS portfolio, building on existing work with IP cores including the MIPS P5600, which is being used in a safety critical design with redundancy for a high-reliability industrial environment.
It also continues Imagination’s safety collaboration with Mobileye. Mobileye’s EyeQ4 SoC for ADAS uses MIPS interAptiv and M5150 CPUs with software self-core test, designed for ASIL B. Its next-gen EyeQ5 SoC for autonomous vehicles is based on the I6500-F CPU and will be manufactured in 7nm FinFET. EyeQ5 will be an open software platform on which customers can deploy their own algorithms – a capability facilitated by MIPS architectural elements including hardware virtualisation. Mobileye SoCs are already available in ADAS systems today.
Elchanan Rushinek, SVP engineering of Mobileye, said: “Our EyeQ5 SoC will be the most advanced solution of its kind for fully autonomous vehicles which will start rolling out in 2020. The ASIL B(D) features in the I6500-F are key to ensuring our chip achieves the highest level of safety. Full cache coherency between CPUs and vision accelerators in the I6500-F makes it an ideal platform for heterogeneous compute, and unique features such as inter-thread communication add to the real-time capability. MIPS multi-threaded CPUs have played a key role in helping successive generations of our EyeQ SoCs achieve significant gains in performance, efficiency and safety.”
Targeting demanding automotive applications
Imagination has established design and safety methodology and processes with documented evidence based on ISO 26262 requirements including safety planning, verification reviews and confirmation measures.
The I6500-F is designed to meet requirements for ASIL B(D) level, allowing the I6500-F to target demanding automotive applications up to ASIL D. The IP was developed as a Safety Element out of Context (SEooC) with a safety lifecycle based on a close collaboration with lead partners and together with a common independent safety assessor, ResilTech S.r.l. The I6500-F design safety lifecycle aligns closely with the component vendor safety lifecycle, based on ISO 26262, 2011 1st Edition standard but already considering best practices for IP from Part 11 to be present in the 2nd Edition of ISO 26262 and already available in the published DIS version.
Dr. Francesco Rossi, automotive safety solution manager for ResilTech, which provides consultancy on functional safety including independent technical safety analysis of hardware and software design based safety-critical systems, said: “As Imagination is developing multiple FuSa IP cores, we’ve been working closely with the MIPS team to ensure its Safety Requirements Specification (SRS) meets the stringent requirements set by its lead customer. Indeed the result is extremely detailed and will be of great value to SoC vendors.”
I6500-F to FortifAI intelligent systems
The I6500-F represents a new class of MIPS processors designed to ‘FortifAI’ next-gen intelligent systems – delivering high system efficiency and scalable computing and raising the bar on functional safety. Customers can be assured that MIPS FortifAI CPUs will provide the high performance and safety features needed for compute-intensive tasks across a wide range of smart safety-critical applications.
Dominique Bonte, Managing Director and Vice President, ABI Research, said: “With the MIPS I6500-F, Imagination is bringing functional safety (FuSa) to high-performance CPU computing required by IoT systems and automotive. Thanks to its safety element out of context for FuSa, its certification process support and its multi-threading for many-core heterogeneous architectures, the I6500-F will enable a faster time-to-market for AI-based autonomous vehicle ASIL-D SoC designs. This will address the needs of the automotive supply ecosystem as it makes a big push towards level 4/5 driverless technology.”
The MIPS I6500-F builds on the popular MIPS I6500 CPU, a 64-bit, multi-threaded, multi-core, multi-cluster CPU that is scalable from embedded to cloud. Both IP cores can coherently implement optimised configurations of CPU cores within a cluster (‘Heterogeneous Inside’) and a variety of configurations of CPU clusters and GPU or accelerator clusters on a chip (‘Heterogeneous Outside’). With features including Simultaneous Multi-threading (SMT) and hardware virtualisation (VZ), the IP offers a range of benefits including 'zero context switching' for applications requiring real-time response. It is also OmniShield-ready, providing a strong foundation for security-by-separation.
The QMS based development process that addresses systematic failures is the foundation of the MIPS I6500-F. Support for run-time LBIST and extensive use of redundancy across critical registers and embedded memories throughout the cores enables detection of transient and permanent faults. Redundancy is extended within the Coherence Manager (CM3) and IO Coherence Unit (IOCU) to complete the protection throughout the MIPS I6500-F multi-core cluster.