Collaboration enables designs on TSMC N5 and N6 processes
Synopsys has announced certification of its digital and custom design platforms for TSMC's N5 and N6 process technologies. Synopsys' long-term collaboration with TSMC has resulted in accelerating next-generation product design for key vertical markets, including high-performance computing (HPC), mobile, 5G, and AI chip designs.
This achievement is the result of an extensive, multi-year collaboration to deliver optimized design solutions that accelerate the path to next-generation designs with innovations providing improvements in power savings and design performance. Synopsys' collaboration with TSMC also extends to 3DIC process technologies, which include CoWoS, InFO, and TSMC-SoIC that enable scalable integration for achieving greater functionality and enhanced system performance.
"TSMC works closely with ecosystem partners to ensure that semiconductor designers can meet next-generation requirements for performance and low power in high-growth markets using TSMC's latest process technologies," said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. "We look forward to continuing our joint efforts with Synopsys to help our mutual customers unleash their silicon innovations for high-performance computing, mobile, 5G, and AI applications."
Certified innovations in multiple Synopsys design tools for HPC and mobile design flows enable designers to take full advantage of TSMC's N6 and N5 process technologies that enhance density, operating frequency, and power consumption. Tools also have been improved to support ultra-low VDD requirements for low power consumption mobile and 5G designs.
As part of the design flow platform certification, results from Synopsys StarRC and PrimeTime signoff solutions were rigorously compared to implementation results. PrimeTime timing reports were also well compared to the golden HSPICE results, to successfully achieve design flow correlation targets that will improve design convergence and shorten overall time-to-market.
"Synopsys' expertise in delivering integrated flows from front-end, physical implementation and signoff combined with TSMC's leadership in process technology, drives the next generation of design innovations in fast-growing markets such as 5G, AI and HPC," said Charles Matar, Senior Vice President of System Solutions and Ecosystem Enablement for the Design Group at Synopsys. "With the TSMC-certified Synopsys design tools, we can provide our customers with a platform that can take full advantage of TSMC's advanced technologies with improved performance, power and scaling."
Key products and features of the Synopsys design platforms included in these collaborations are:
Digital design solutions
- Fusion Compiler and IC Compiler II place-and-route
- PrimeTime timing signoff
- PrimePower power signoff
- StarRC extraction signoff
- IC Validator physical signoff
- NanoTime custom timing signoff
- ESP-CV custom functional verification
- QuickCap NX parasitic field solver
SPICE simulation and custom design
- HSPICE, CustomSim, and FineSim simulation solutions
- CustomSim reliability analysis
- Custom Compilercustom design