The new ClearSignal RF agnostic design broadens SoC designers’ choice to immediately add Digital Radio capability to mobile devices, while keeping the required low power consumption. This ClearSignal implementation takes advantage of Tensilica’s ConnX Vectra LX DSP Engine and other architecture optimizations for achieving a typical DAB channel reception at clock rates as low as 50 MIPS.
The new version implements all the broadcasting standards supported by ClearSignal: DAB, DAB+, T-DMB, DRM and in future DRM+, while exhibiting its renowned high performance.
Tensilica cores and ClearSignal SDR-based Digital Radio match well in their quest and achievement of high performance radio reception, said Ben Gagin, EtherWaves CEO. The successful porting to Tensilica’s core follows our winning strategy to support the leading chip architectures, thereby offering additional flexibility to our customers, he added.
Digital Radio is clearly the future of the radio market and we are delighted to have the opportunity to contribute with the rapid development of this new EtherWaves multi-standard solution, stated Larry Przywara, Tensilica’s senior director of multimedia marketing. This successful achievement proves that our architecture has the programmability and speed/power/efficiency necessary to help designers meet the high performance and cost-effectiveness requirements of modern Digital Radio receivers.
Tensilica’s Xtensa dataplane processors can be customized for applications such as digital audio, baseband DSP, and many other functions that most general-purpose processor cores can’t efficiently perform. By customizing the processor using Tensilica’s automated process, designers can get the best combination of low power, high performance and efficiency for their designs.
The new ClearSignal version is available for licensing from EtherWaves, who also provides Digital Radio integration services for fast and cost effective implementation.