Cadence optimises digital full flow for Arm Cortex-A78

To drive Cortex-A78 and Cortex-X1 adoption, Cadence has delivered a comprehensive, digital full flow Rapid Adoption Kit (RAK) that helps customers optimise power, performance, and area (PPA) and boost overall productivity.

In addition, the Cadence Verification Suite and its engines have been optimised for the creation of Cortex-A78 and Cortex-X1 CPU-based designs, providing engineers with enhanced verification throughput.

Digital full flow RAK

The Cadence digital full flow RAK has been finely tuned to provide optimal power and performance and supports both 7nm and 5nm foundry process nodes. The fully integrated Cadence RTL-to-GDS RAK includes the Genus Synthesis Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff and ECO Solution, and the Voltus IC Power Integrity Solution. Some of the key features incorporated into the digital full flow are as follows:

• Cadence iSpatial technology unifies the Genus Synthesis Solution and Innovus Implementation System to deliver better PPA and faster design closure.
• RTL-to-signoff activity vector-driven power optimisation enables designers to achieve lower power for critical workloads.
• Simultaneous power-integrity and timing signoff closure using Cadence’s unique data model integrates implementation, timing signoff and IR drop signoff engines, which is essential for designing on 5nm and 7nm advanced-process nodes.

Verification suite and engines

The powerful combination of the Cadence Verification Suite and its engines have also been tuned and used to support Arm Cortex-A78 and Cortex-X1 CPU-based designs and augment verification throughput. The Cortex-A78 and Cortex-X1 CPU-optimised suite includes the Cadence Xcelium Logic Simulation Platform, Palladium Z1 Enterprise Emulation Platform, JasperGold Formal Verification Platform and vManager Planning and Metrics and Cadence Arm AMBA VIP, including ACE and CHI-D CIP and the Perspec System Verifier Arm library.

Some of the key technologies supporting Cortex-A78 and Cortex-X1 development are the JasperGold Formal Property Verification (FPV) and Sequential Equivalence Checking (SEC) Apps, which have been used in lock-step verification, checking across multiple cores for deterministic results. Furthermore, the Verification Suite’s dynamic engines have been used by mutual customers for verification and early software development.

“Through our continued collaboration with Cadence, we’re enabling our customers to achieve more performance, efficiency, scalability, and ultimately, mobile product differentiation,” said Paul Williamson, Vice President and General Manager, Client Line of Business, Arm. “The Cadence digital full flow RAK and Verification Suite and engines provide customers with the foundation they need to develop next-generation mobile products with our Cortex-A78 and Cortex-X1 CPUs, which will enable our partners to transform smartphone experiences in the 5G era.”

“Over the course of the past year, we’ve worked closely with Arm to ensure that our digital full flow RAK and Verification Suite and engines are optimised for the Cortex-A78 and Cortex-X1 CPUs,” said Nimish Modi, Senior Vice President, Marketing and Business Development at Cadence. “Customers are consistently under pressure to deliver innovative mobile technologies within tight timelines, and the collaboration ensures that they can implement the Cortex-A78 and Cortex-X1 CPUs more quickly and achieve the desired end product goals and quality.”

The Cadence digital full flow provides customers with a fast path to design closure and better predictability. The Cadence Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that improve verification throughput. The Cadence flow and tools support the broader Cadence Intelligent System Design strategy, enabling customers to achieve design excellence.