CSR Accelerates Low-Power, Mixed-Signal Chip Tapeout with Cadence Encounter Digital Implementation System

The Cadence digital flow enabled CSR to tape out a 40-nanometer low-power Bluetooth and Wi-Fi combo chip speedily and efficiently, delivering excellent results in power, area and time-to-market.

The multi-radio chip included several analogue blocks, multi-million gate instances, multiple voltage islands and complex switchable power domains. The Cadence hierarchical Common Power Format based comprehensive power intent methodology allowed CSR to precisely capture and manage power intent throughout the flow. The EDI System helped reduce power domain crossings and made designing with multiple supply voltages much easier. The net result was significant power savings while optimizing area and performance automatically. For verification, CSR performed power-aware simulation with IES, and formal checking using CLP, to confirm the correct implementation of its power architecture against the golden CPF.

In addition, the EDI System’s timing and signal integrity engineering change order flow helped to significantly accelerate the sign-off correlation fixing cycles leading to faster timing convergence and signal integrity signoff. The resulting productivity improvements helped shave off several weeks from CSR’s design schedule.

“In another recent multi-radio chip tapeout, the Cadence EDI System and low-power design methodology enabled us to effectively implement and optimize a consistent set of design and multi-supply-voltage power domain constraints across a complex digital-driven mixed-signal hierarchy,” said Steven D. Gray, Ph.D., CTO of CSR. “We gained significant power savings and achieved faster timing and signal-integrity signoff. As a result of this tapeout success, we have confidence in using the Cadence EDI System and CPF-driven low-power flow across all of our mobile connectivity and automotive designs.”

The Cadence Encounter RTL-to-GDSII flow helps design teams optimize power, performance and area for the world’s most sophisticated high-performance, low-power designs at advanced nodes. The integrated Cadence flow includes Encounter RTL Compiler, EDI System, and signoff-proven Cadence QRC Extraction, and Encounter Timing System. The new GigaOpt optimization engine inside EDI System produces high-quality results faster than traditional optimization engines by harnessing the power of multiple CPUs. In addition, the integrated CCOpt technology unifies clock tree synthesis with logic/physical optimization resulting in significant power, performance and area improvements.

“The demand for low-power mixed-signal designs for consumer electronics is skyrocketing. The CSR design team chose Cadence for our mature and comprehensive low-power solutions that meet the most pressing challenges of complex SoC design,” said Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “The Encounter digital flow provided a predictable design closure path, meeting and exceeding CSR’s stringent design and time to market requirements. We worked closely with CSR to help them achieve tapeout success for this innovative low-power and mixed-signal SoC.”