Design

Axell chooses Synopsys for graphics IC designs

16th December 2015
Nat Bowers
0

Axell, a fabless design company of graphics chips for interactive entertainment and industrial embedded systems, has switched to Synopsys' Design Compiler RTL synthesis solution for their IC designs. Achieving smaller die area with high engineering productivity are critical goals for Axell to deliver competitive products to their target markets. To achieve these goals, Axell evaluated available RTL synthesis solutions and selected the Design Compiler solution, including DC Explorer, based on results delivering 5% area reduction coupled with high design performance and fast runtime.

Atsushi Kikuchi, Senior Manager, Axell, commented: "With their next-gen interactive entertainment products requiring higher resolution graphics capabilities, our customers are looking to Axell to deliver increasing design performance with improved cost effectiveness. Following an evaluation of available RTL synthesis solutions, we selected Synopsys' Design Compiler as a result of its ability to shrink our design size by 5% while achieving fast design closure. We are also adopting DC Explorer to give us additional capabilities for fast, early RTL exploration to quickly and efficiently perform what/if analyses of various design configurations before committing to our final design. We are deploying these tools for our next-gen chips targeting an advanced manufacturing process."

Synopsys' Design Compiler family of products maximises design productivity with its complete solution for RTL synthesis and test. Underpinning the Design Compiler family, the DC Ultra synthesis solution concurrently optimises for timing, area, power and test and includes topographical technology to reduce costly design iterations. DC Explorer enables early RTL and floorplan exploration to accelerate development of high-quality RTL and constraints, leading to faster synthesis and place and route. Design Compiler Graphical uses advanced optimisations and shared technology with the IC Compiler and IC Compiler II place and route solutions to deliver best-in-class quality of results for the most challenging designs at all process nodes. In addition, Design Compiler Graphical enables RTL designers to predict, visualise and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. Design Compiler Graphical also produces physical guidance to IC Compiler and IC Compiler II that tightens timing and area correlation and speeds-up placement runtimes.

"In the interactive entertainment and industrial embedded systems markets that Axell serves, high performance and cost effectiveness are key ingredients for their product success. Design Compiler's advanced optimisation technologies coupled with DC Explorer's early RTL analysis capabilities enable Axell to achieve design size reduction while meeting the high performance required for their customers' next-gen products," added Bijan Kiani, Vice President of Marketing, Design Group, Synopsys.

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