Avago’s embedded SerDes intellectual property (IP) core offers extremely low jitter, making it possible to integrate as many SerDes channels as needed onto a single 65-nm CMOS (complementary metal oxide semiconductor) chip, each operating at up to 12.5 Gbps. Additionally, the new SerDes core features Avago’s proprietary clockless Decision Feedback Equalization, on-chip BERT for channel bit error rate optimization, LC-based oscillator for improved power-supply noise rejection, and 1149.6 AC-Extest for testing AC-coupled connections.
“This technology advancement, representing our fifth generation SerDes core, will continue to provide networking and computing OEMs with competitive advantages,” said James Stewart, vice president and general manager of Avago Technologies’ Enterprise ASIC division. “Our customers can rely on us to deliver high-bandwidth systems with superior reliability, and reduced size, complexity and cost.”
This core is the latest in Avago’s broad embedded SerDes offering which include cores planned for use in Fibre Channel, XAUI/CEI, XFI, 802.3ap and PCI-Express applications.
Avago Technologies incorporates testing capabilities as early as the definition of system-level architecture and accounts for in-circuit manufacturing test, functional test, system turn-on and debug, and field diagnostics. The result is faster time to market of reliable high-bandwidth networking and storage systems.