Design

IJTAG interoperability demos at ITC in Anaheim

6th October 2015
Mick Elliott

At the International Test Conference (ITC) in Anaheim, ASSET InterTech and Cadence Design Systems are demonstrating the interoperability of their IEEE 1687 Internal JTAG (IJTAG) tools, which enable the re-use of embedded intellectual property (IP) both internally on chips and externally onto system boards.

The key value of the IJTAG embedded instrumentation standard is the use of embedded IP in chips to debug, characterize and validate the internal operations of the devices themselves and then re-use this same IP to drive validation and structural tests externally from the host chip onto the circuit board for advanced system diagnostics.

“Several shared customers motivated our two companies to demonstrate the interoperability of our tools,” said Tim Caffee, ASSET’s vice president of design validation and test. “Both chip and system-level DFx engineers have found tremendous value in the ability to re-use embedded instruments and move back and forth diagnosing both chip operations and system performance. Plus the re-use of instruments already present in silicon holds great value for chips, systems and products throughout every phase of their lifecycles. We’re very glad Cadence has joined the growing ecosystem of IJTAG tools.”

ASSET’s ScanWorks IJTAG tool complements the Cadence Encounter Test tool’s ability to insert various types of IJTAG-compatible IP into silicon. Internally to the chip, this IP might monitor operating parameters or confirm the functionality of the device. Externally from the chip, embedded IJTAG IP could be re-used to drive data across serdes buses for performance testing or to analyse the system’s operating margins.

Another example would be a logic built-in self-test (BIST) controller that acts as an embedded instrument for validating internal digital logic. It could then be accessed from the circuit board to retest the logic within the chip.

“The Encounter Test tool delivers a comprehensive design for test (DFT) and automated test pattern generation (ATPG) solution for today’s complex ICs and SoC designs,” said Paul Cunningham, vice president of research and development in the Digital and Signoff Group at Cadence. “As chips and, particularly, SoCs, have become more complex, embedded

IJTAG-accessible instruments are taking on a greater role in characterizing the internal operations of these devices. The interoperability between the Encounter Test tool and ASSET ScanWorks allows our mutual customers to re-use the IP for external debug, validation and test, which increases the value of the IJTAG IP.”

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