Architecture for HPC devices using nanosheet fabrication

Institute researchers fabricated GAA nanosheet transistors with seven levels of stacked silicon channels, more than twice as many as state-of-the-art today, with widths ranging from 15nm to 85nm. The results were summarized in the paper, ‘7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing’, presented virtually during the 2020 Symposia on VLSI Technology & Circuits, June 14-19.

CEA-Leti scientist Sylvain Barraud, one of the authors of the paper, said the seven levels of stacked nanosheet GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show excellent gate controllability with extremely high current drivability (3mA/μm at VDD=1V), and a three-x improvement in drain current over the usual two levels stacked nanosheet GAA transistors.

“By increasing the number of stacked-channels, we increase the effective width of the device for a given layout footprint,” he explained. “Increasing the effective width induces higher drive current. This is why the DC performance of our devices is better than leading-edge devices.”

Barraud said CEA-Leti’s demonstration was based on a ‘replacement metal-gate’ process developed for FinFET.

“We added specific modules for GAA structures on this FinFET route and we showed that for the same surface occupation we can propose an alternative to FinFET technology due to a gate-all-around configuration,” Barraud said. “In fact, GAA structures offer many advantages over FinFET, such as better gate control and higher DC performance, thanks to higher effective channel width. In addition, the wide range of variable nanosheet widths allows more design flexibility, which is not possible for FinFET because of its discrete number of fins.”