Analog front end reference design for high-speed oscilloscope
This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200.
This feature is also used to minimise mismatches typical of interleaved ADCs: maximising SNR, ENOB, and SFDR performance.
A low phase noise clocking tree with JESD204B support is also featured on this reference design, and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesiser and jitter cleaner.
Features
- Sampling rate up to 12.8GSPS, using timeinterleaved 12-bit RF-sampling ADCs.
- Analog front end support up to 6-GHz bandwidth.
- Fine sample clock phase adjustment (19 fs resolution).
- Phase synchronisation of multiple ADCs.
- Companion power reference design with a >85% efficiency at 12V input.
- JESD204B supporting eight, 16, or 32 JESD lanes, data rates up to 12.8Gbps per lane.
To find out more, click here.
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APV1111GVY
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