Agile Analog selects EnSilica for SoC development

6th July 2020
Alex Lynn

Agile Analog has announced that they have worked with EnSilica, to both fabricate and test their latest analogue IP products, and to validate that their advanced product delivery processes provide maximum benefit to Agile Analog’s end customers.

The project speeds up the process of proving and qualifying analogue IP, and reduces the time-to-market and risk of IC development cycles through a revolutionary top-down delivery of initial IP views.

The integration of analogue IP onto a complex silicon chip is a time-consuming process that is exacerbated by the variable quality of currently available analogue IP products. Analogue circuits are also very sensitive to their on-chip surroundings so issues during integration and test can lead to reliability problems during the manufacture and mass production of such chips. Finally, waiting until the end of analogue IP delivery can both slow down chip planning work, and mean that critical customer feedback is not available until it’s too late.

Agile Analog has developed an in-house system to automatically generate analogue IP (including all associated IP product deliverables) to a high quality, according to customer specifications, and on any silicon process technology. This system produces a high-quality final IP delivery package (FDP), as well as an initial delivery package (IDP). The IDP is available very early and allows customers time to integrate it into their chip development process and provide feedback to be implemented in the FDP.

EnSilica’s expertise in the design of custom analogue, mixed-signal and digital chips was critical to developing a chip architecture together with a re-usable test platform that Agile Analog will use to test and validate their latest analogue IP products.EnSilica has integrated a number of Agile Analog’s IP products, including their latest configurable analogue-to-digital converter (ADC) IP and bandgap voltage reference IP, onto this System-on-Chip for fabrication in TSMC’s 28nm CMOS technology.

“What Agile Analog has achieved is impressive,”said Ian Lankshear, CEO at EnSilica.“The high quality of their automatically generated IP deliverables really does save integration time and effort and will benefit all their customers. Thanks to their comprehensive documentation, the integration of their analogue IP onto an SoC and the development of a test setup and procedure was effortless for our engineers, and most of our work could be done using the IDP, so we were able to get a significant amount of work done early.”

Tim Ramsdale, CEO at Agile Analog, added: “EnSilica’s extensive chip design expertise was amply demonstrated in the re-usable SoC design and test solution they created. This work will be instrumental to Agile Analog and will allow us to prove more of our analogue IP in silicon quickly and efficiently. The project also served as a pipe-cleaning exercise and EnSilica’s knowledgeable feedback and recommendations have allowed us to improve our products further.”

Agile Analog’s use of design automation to generate analogue IP results in products that are guaranteed to be consistent and of high quality. Their innovative approach is transforming the semiconductor market by producing analogue IP that is customised to the application’s requirements and is available on any semiconductor process. The project with EnSilica enables Agile Analog to silicon-prove their analogue IP products more efficiently. This will enable Agile Analog’s customers to take their chips into production faster and more reliably.

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