Barco Silex FPGA Design Speeds Transactions In Atos Worldline Hardware Security Module
Barco Silex announce that Atos Worldline uses a Barco Silex FPGA crypto platform in its ADYTON. The ADYTON, which recently received an iF product design award in addition to its red dot product design award, integrates Barco Silex’s IP to achieve RSA and ECC performance levels of over 7000 op/s in RSA CRT and FIPS 140-2 Security level 4 certification.“W
“Achieving over 7000 op/s on an FPGA running at 250 MHz is quite an achievement and shows how powerful our crypto IP platform is,” commented Sébastien Rabou, Product Manager, Barco-Silex. “Today there is an increasing need for security in data communications systems, to handle financial transactions including mobile and online payments as well as to protect data and content. These systems must offer very high levels of protection and manage large numbers of transactions at high speed. The ADYTON shows that hardware security modules using our IP and FPGA can achieve the required performance cost-effectively.”
Barco Silex offers a broad portfolio of flexible and scalable security IP cores for symmetric and asymmetric cryptography. For Atos Worldline, Barco Silex drew on its BA414E (Public Key crypto Engine), BA413 (Hashing engine) and BA431 (True Random Number Generator). Combined with the company’s expertise in FPGA, ASIC and SoC design, this delivered an autonomous platform supporting key generation, signature verification, prime number and FIPS compliant random number generation.
The high level of flexibility and scalability of Barco Silex crypto IP enables customers to optimally balance gate count and performance by selecting appropriate core options. And the highly pipelined and optimized architectures generate the fastest and smallest solutions on the market.
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