I/O interfaces include USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC and Smart Card. The core is also equipped with a DoCD hardware debugger featuring Instruction Smart Trace (IST) technology, which only captures the addresses of executed instructions that are related to the start of tracing, conditional jumps and interrupts. This method not only saves time but also increases the size of the IST buffer and extends the trace history. Captured instructions are read back by DoCD-debug software, analysed and then presented to the user as ASM code and related C lines.
The DQ8051 is delivered with a fully automated testbench and a complete set of tests, enabling easy package validation at each stage of the SoC design flow. The technology independent can be used in both ASIC and FPGA technologies.
