As logic and memory nodes scale, performance of these advanced interconnects is negatively impacted by increasing interconnect resistance. Furthermore, voids that occur in heavily scaled vias severely impact yield. Imec’s industrial affiliation program on advanced interconnects is exploring novel metallisation methods to solve these issues.
One way to solve the problem is to identify integration and metallisation alternatives that provide resistance benefits over conventional technology without compromising reliability and yield. Together with Lam Research, a Co ELD technique was demonstrated as a feasible method for highly selective bottom-up contact fill and via prefill with cobalt as an alternative metal to copper.
Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio 4.5)
The high selectivity of the ELD process, at lower cost compared to Chemical Vapor Deposition (CVD), intrinsically ensures a good metal-to-metal interface and paves the way to void-free via filling and increased yield. Trench fill yield and line resistance may also benefit from the de-coupling of line and via aspect ratios, permitting the design of each for optimum resistance/capacitance. Therefore, Co prefill ELD has the potential to enable future scaling of advanced logic and memory technologies.
The results were achieved in co-operation with imec’s key partners as part of its core CMOS programmes: GlobalFoundries, Intel, Samsung, SK Hynix, Sony, TSMC, Amkor, Micron, Utac, Qualcomm, Altera, Fujitsu, Panasonic, and Xilinx.