Using either a single 122.88-MHz or 153.6-MHz fixed reference clock frequency, the new SerDes can support Common Public Radio Interface (CPRI™) and Open Base Station Architecture Initiative (OBSAI) rates. Also, the TLK6002’s 20-bit parallel single-ended interface connects easily to field-programmable gate arrays (FPGAs). When compared with FPGAs featuring high-speed serial links, a more economical FPGA and TLK6002 combined can provide significant system cost savings
Key features and benefits of the TLK6002:
· Receiver equalization and transceiver pre-emphasis improves signal integrity by compensating for amplitude losses in cables and for ISI (inter-symbol interference), enabling a trace reach of greater than 50 cm.
· Integrated automatic CPRI/OBSAI rate sensing “self-tunes” to the system setting, eliminating the need for additional hardware or software.
· Integrated high-accuracy latency measurement (0.6510 ns at 6.144 Gbps) relieves designers’ workload by simplifying the system design.
· Supports CPRI/OBSAI data rates: 0.6144, 0.768, 1.2288, 1.536, 2.4576, 3.072, 4.9152 and 6.144 Gbps.
· The TLK6002 complements many TI digital signal processors (DSPs), data converters and clock products.