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The D2692 UART IP Core Offers More

The D2692 Dual Universal Asynchronous Receiver/Transmitter is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in just one single package. DCD’s IP Core interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. – Additionally, each receiver and transmitter can select its operating speed – says Jacek Hanke, DCD’s CEO – as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The opportunity to program independently the operating speed of the receiver and transmitter, denotes the UART particularly attractive for dual-speed channel applications like eg clustered terminal systems.

Communications

5 September 2013

byNews Desk

Every receiver is being equipped with fifo to minimize the potential of receiver over-run and to reduce interrupt overhead in interrupt driven systems. Moreover, the D2692 UART IP Core ensures a flow control capability, to disable a remote DUART transmitter, when the receiver buffer is full. To make this design even more functional, there’ve been added multipurpose 7-bit input port and a multipurpose 8-bit output port. They can be used as general purpose I/O ports or can be assigned to specific functions (eg clock inputs or status/interrupt outputs) under program control.

Key features:

Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
Configuration capability
Dual full-duplex independent asynchronous receiver/transmitters
8 character FIFOs for each receiver and transmitter
Programmable data format:
- 5 to 8 data bits plus parity
- Odd, even, no parity or force parity
- 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
16-bit programmable Counter/Timer
Programmable baud rate for each receiver and transmitter selectable from:
- 27 fixed rates: 50 to 230.4k baud
- Programmable user-defined rates derived from a programmable counter/timer
- External 1X or 16X clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode:
- Normal (full-duplex)
- Automatic echo
- Local loopback
- Remote loopback
- Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
Multi-function 7-bit input port:
- Can serve as clock, modem, or control inputs
- Change of state detection on four inputs
Multi-function 8-bit output port:
- Individual bit set/reset capability
- Outputs can be programmed to be status/interrupt signals
- FIFO states for DMA and modem interface
Versatile interrupt system:
- Single interrupt output with eight maskable interrupting conditions
- Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
- Each FIFO can be programmed for four different interrupt levels
- Watch dog timer for each receiver
Automatic wake-up mode for multidrop applications
Start-end break interrupt/status
Detects break which originates in the middle of a character
Power down mode
Receiver timeout mode