PCIe clock buffers deliver 70% lower additive jitter

13th March 2014
Nat Bowers

Compared to competitive devices, the LMK00334 and LMK00338 clock fanout buffers from Texas Instruments deliver 70% lower additive jitter and significantly higher supply noise rejection. The pair of 4-output and 8-output high-speed current steering logic (HCSL) devices are suitable for high-speed communications, networking and data centre systems, including servers, switches and routers.

Providing system designers with ample jitter margin over the PCIe 3.0 specification, both devices are supported in TI’s WEBENCH Clock Architect to help simplify clock tree design. TI have claimed that the fanout clock buffers offer the industry's lowest additive jitter of 30fs at 100MHz (PCIe 3.0) and 86fs at 12KHz-20MHz (HCSL at 156.25MHz). This gives designers more flexibility in timing budget allocation for the entire link.

The high power supply rejection ratio (PSRR) of -75dBc at 100MHz provides improved jitter performance and better noise immunity than competitive devices, enabling robust signal integrity. Two universal inputs operate at up to 400MHz and offer compatibility with any input type, including CML, LVPECL, LVDS, SSTL, HSTL, HCSL, or single-ended clocks and crystal oscillators. Additionally, the LMK00334 and LMK00338 feature pin-mode control which makes it easy for system designers to turn an individual output bank on and off.

The LMK00334 and LMK00338 can be combined with the CDCM9102 and the CDCM6208 PCIe clock generators to create a high-performance clock tree solution. TI’s clock distribution and fanout buffers give clock tree designers the flexibility, performance and advanced features they need to address a broad range of communications, networking, industrial and consumer applications.

Engineers can accelerate their clock tree designs with the LMK00334 and LMK00338, by using TI’s WEBENCH Clock Architect. It is the industry’s first timing design tool that can recommend and simulate a system clock tree solution from an exhaustive database of devices. It features phase-locked loop filter design and the ability to simulate phase noise of the output clocks. The tool also provides the ability to simulate end-to-end jitter performance for the complete clock tree.

Both the LMK00334 and the LMK00338 utilise the LMK00338 evaluation module to verify functionality and performance specifications. IBIS simulation models are also available for the LMK00334 and LMK00338.

The LMK00334 is available now in a 5x5mm, 32-pin WQFN package for a suggested retail price of $1.20 (USD) in 1,000 unit quantities. The LMK00338 is available now in a 6x6mm, 40-pin WQFN package for a suggested retail price of $1.80 (USD) in 1,000 unit quantities.

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